In a number of applications for precision analog circuits, such as converters or precision voltage references, the absolute-value tolerances of circuit components such as resistance are important. However, it is difficult to guarantee absolute-value tolerances associated with semiconductor or thin-film resistors due to unpredictable variations in manufacturing process steps. Additional steps must be taken to trim the on-chip resistor network after its fabrication, to meet a given absolute-value tolerance. One common adjustment method is by the use of fusible links.
A fuse can simply be a short section of minimum-width metal or polysilicon connected between two bond pads. It is programmed or blown, by passing a large current between the bond pads, causing the fuse material to vaporize. After programming, the fuse becomes an open circuit.
Several fuses in combination provide additional trimming resolution. In a typical voltage trimming across a resistor, the resistors are connected in series for binary-weighted adjustment. These links initially short-circuit all the taps together, but they can be selectively open-circuited by blowing them.
One typical application of voltage trimming is the output voltage adjustment for Low Dropout Voltage Regulator (LDOR). Output accuracy is a stringent requirement for LDOR, and the output voltage Vout is usually directly proportional to the reference voltage Vref. Thus, it is necessary to minimize the error in Vref to maintain the precision for Vout. Vref is usually a band-gap reference voltage and better accuracy of Vout can be achieved by resistor trimming.
FIG. 1 shows a trimming circuit 100 applying conventional fuse structure to Vref trimming for bandgap reference circuit to compensate for the device parameter variation due to manufacturing process. Vref is governed by the equation:
      V    ⁢                  ⁢    ref    =            (                        R          ⁢                                          ⁢          3                          R          ⁢                                          ⁢          2                    )        ⁡          [                        V          ⁢                                          ⁢          e          ⁢                                          ⁢          b          ⁢                                          ⁢          1                +                              (                                          R                ⁢                                                                  ⁢                2                                            R                ⁢                                                                  ⁢                1                                      )                    ⁢                      ln            ⁡                          (              N              )                                ×          V          ⁢                                          ⁢          t                    ]                      Where Veb1 is the base emitter voltage of pnp 109;                    Vt is the thermal voltage which equals to kT/q;            k=Boltzmann's constant;            T=absolute temperature; and            q=electronic charge;                        
Therefore, one of the parameters that can be varied on chip to alter the Vref value is the resistance R1.
When Vref measured at the wafer level is different from the desired value, fuses are selectively blown by applying voltage across them, thus adjusting the overall resistance to fine tune Vref accuracy.
In FIG. 1, all fuses initially are conductive and the resistor network has an overall resistance close to R1. Assuming the resistor network is required to be trimmed to an additional resistance of RMSB, the fuse 102 in parallel with resistor RMSB has to be blown. This can be performed by applying a high voltage source 101 to pads across fuse 102 and hence a high current flowing through fuse 102 to blow it.
The major drawback of existing structure and method is yield loss due to stress to on-chip active devices. Due to process variation, the resistance of the fuse fabricated may happen to be higher than expected and the conventional method may not be able to supply sufficient power to cut the fuse. Even higher voltage may be used to ensure the fuses are blown. However, the on-chip circuitry coupling to the fuses is also exposed to such extraordinarily high voltage that may cause damage to the circuitry, especially the active devices.
In the foregoing example, the high voltage applying across fuse 102 propagates to node 104 through resistor 103, inducing over-voltage stress on all devices connecting to node 104, including transistor 105 and comparator 106. In addition, the high voltage further propagates through resistor 107 to node 108 if resistance is not large enough. Accordingly, devices 109, 110 connecting to node 108 may also be vulnerable to the high voltage. Either the voltage is not high enough to blow the fuse, or the voltage is too high and damages the on-chip devices, both eventually result in substantial yield loss in mass production.
Consequently, a need exists for an improved fuse cell and programming method that can avoid the fuse unintentionally remaining intact and circuits damaging by programming voltage.